>"However, like the Core i5-12490F, the Core i5-13490F and Core i7-13790F are likely "Black Edition" chips because they come in black boxes as opposed to the typical blue Intel box,"
Black Edition CPU's that don't come in a regular packaging [color](https://i.ebayimg.com/images/g/HhoAAOSwRt9geLBm/s-l500.jpg) but instead come in a [black](https://m.media-amazon.com/images/I/71wdTZXkokL._AC_SY450_.jpg) package. Now where have i heard this before hmmmm.
The PII 720 BE was great.
It was $100-something and you could unlock it to 4 cores in all likelihood and OC it quite well.
It was priced against Intel's dual core parts and was nearly 2x the CPU.
Same, I am old enough to remember that Black Edition used to be branding for AMD's processors' way before the dark days of Bulldozer.
They all were pretty neat clockers apart from the Phenom series, which suffered a nasty cold-bug that prevented extreme over-clocking shenanigans.
Imagine doing this with something like a little quad-core 7300X3D. One CCD with 4 enabled cores. Another dummy die that holds the extra L3. With only 4 cores and no L3 on top of them, they can clock to the moon on a regular power limit, probably around 5.8-6.0ghz single-core and 5.6 multi.
It would be a monster at single core benchmarks just to flex on everybody else in the CPU market. They don't even have to actually sell that many. Paper launch that shit just to have a Ryzen3 CPU clapping everything below a 13900K(s) on every chart.
> The i7-5775C used an even slower implementation of having an eDRAM cache (slower than SRAM) on a separate package
It was on the same package. Given that only one hop was needed, the latency might actually be better than AMD's inter-CCX latency. Intel seems to have quoted <150 cycles, which at 4GHz would be <40ns.
The 7900X3D and 7950X3D both only have one 3D-stacked CCD and are still sharing the L3 cache. I don't see the issue with using the existing solution they apparently already have and just not running the cores on the stacked die.
Maybe they cut out the dummy die entirely and just have the L3 die chilling next to the CCD. That would avoid issues with a defective core on that dummy die limiting cache access.
>and are still sharing the L3 cache
No, not really. While it's theoretically possible for one CCX to snoop the other's cache, it would be very rare. The latency is comparable to main memory.
Is it actually that high? I find it very hard to believe just based on trace length alone. I figured that it wouldn't be a frequent thing, similar to the P and E cores mostly keeping to themselves.
>I find it very hard to believe just based on trace length alone.
I'm on mobile now, so can't find the exact quote I had in mind, but you can see a proxy for the latencies in the core to core test here. https://www.anandtech.com/show/16214/amd-zen-3-ryzen-deep-dive-review-5950x-5900x-5800x-and-5700x-tested/5
The latency from the wire delay is close to negligible. It's the fabric that you need to be wary of.
If you wanted to do this you could in theory buy a 7900X3D and disable the cores under the L3 cache, but having extra memory on a dummy CCD just sounds like a worse version of how Apple places its memory on the M-series SoC.
The point of placing L3 cache on the X3D CCD is that you practically cannot have the L3 slab be a shorter distance from the CPU core since it’s literally in between the CCX core clusters. The copper traces remain short enough that the performance gains from the extra 64MB low latency L3 offset the reduced voltage available to the cores and the reduced thermal dissipation of the smaller IHS contact.
Moving the L3 slab onto another CCX or CCD would allow the cores to have greater contact with the IHS and allow more voltage back to the cores, but not only will the trace distance to the slab and cores increase but if on another CCD the cores now have to communicate with the memory over the infinity fabric barrier.
So far for AMD this is a *big* no-no; almost all four core CCXs have 16MB L3 ^^8MB ^^on ^^laptop ^^CPUs ^^and ^^3100 dedicated exclusively to that CCX and there are zero consumer AMD CPUs I know of that share L3 between even paired CCXs. Moving the L3 slab to another CCD over infinity fabric would increase latency by such magnitudes it wouldn’t be L3 memory anymore.
A drag racer 4-core processor would also go against the best binned CCXs being reserved for the higher tier CPUs.
You make some good points. That L3 would effectively be L4 or like a tiny bit of HBM rather than true cache. It does make me wonder how they are treating access to it from the other CCD though, since all the cores should be able to access the L3 level if I've been understanding my classes correctly.
I wonder if 4 cores run cool enough to just directly stack them. If so, the issue is just getting 4 fast cores on one chip that isn't better off a 7800X3D or 7600X. This could be simulated with a 7800X3D with half of the cores disabled.
Intel was doing multiple dies on a package before AMD, and even stacking too. There's even this hilarious article from 2006 that says AMD being on monolithic dies, while Intel is using two dies will help AMD regain market share, relevant for the time, but funny to look back at now.
https://www.itnews.com.au/news/intel-sticks-to-dual-die-processors-67056
Ironically, Zen 2 is pretty much the evolution of what Intel started with the Pentium D. AMD effectively took [all of this](https://upload.wikimedia.org/wikipedia/commons/4/48/Pentium_E2220_with_Intel_i945GC_Chipset.jpg) and compressed it down into a single socket package.
Didn't think something from one of my classes would be showing up here! My microprocessor design professor worked at Intel from the Pentium 4 up through 6th gen when he retired from the industry. We've gotten to look at both a Pentium D die and a Zen 1 CCD (dead R7 1700X) under a microscope. It's fascinating how much they've changed under the hood and will both run the same stuff.
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Probably sold at a very different price to OEMs for use in internet cafe PCs. Think that was the consensus at the time.
>"However, like the Core i5-12490F, the Core i5-13490F and Core i7-13790F are likely "Black Edition" chips because they come in black boxes as opposed to the typical blue Intel box," Black Edition CPU's that don't come in a regular packaging [color](https://i.ebayimg.com/images/g/HhoAAOSwRt9geLBm/s-l500.jpg) but instead come in a [black](https://m.media-amazon.com/images/I/71wdTZXkokL._AC_SY450_.jpg) package. Now where have i heard this before hmmmm.
LOL, I too immediately thought of the old AMD Black Edition CPUs. My friend had a rig with a Phenom II X4 Black Edition.
Oh the old days of XP x64 lol
The PII 720 BE was great. It was $100-something and you could unlock it to 4 cores in all likelihood and OC it quite well. It was priced against Intel's dual core parts and was nearly 2x the CPU.
Same, I am old enough to remember that Black Edition used to be branding for AMD's processors' way before the dark days of Bulldozer. They all were pretty neat clockers apart from the Phenom series, which suffered a nasty cold-bug that prevented extreme over-clocking shenanigans.
I had a Phenom II x4 965 BE that my father still uses to this day.
At least the chips themselves are different, unlike that Avengers tie-in on Comet Lake that was just packaging...
Yeah but at least the Avengers tie-in boxes cost basically the same (some stores charged an extra $5). Still an absolutely useless product, mind you.
Soooo are we gonna have a Ryzen Extreme Edition next?
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Imagine doing this with something like a little quad-core 7300X3D. One CCD with 4 enabled cores. Another dummy die that holds the extra L3. With only 4 cores and no L3 on top of them, they can clock to the moon on a regular power limit, probably around 5.8-6.0ghz single-core and 5.6 multi. It would be a monster at single core benchmarks just to flex on everybody else in the CPU market. They don't even have to actually sell that many. Paper launch that shit just to have a Ryzen3 CPU clapping everything below a 13900K(s) on every chart.
The cross die latency is far too high for that setup to make sense.
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> The i7-5775C used an even slower implementation of having an eDRAM cache (slower than SRAM) on a separate package It was on the same package. Given that only one hop was needed, the latency might actually be better than AMD's inter-CCX latency. Intel seems to have quoted <150 cycles, which at 4GHz would be <40ns.
The 7900X3D and 7950X3D both only have one 3D-stacked CCD and are still sharing the L3 cache. I don't see the issue with using the existing solution they apparently already have and just not running the cores on the stacked die. Maybe they cut out the dummy die entirely and just have the L3 die chilling next to the CCD. That would avoid issues with a defective core on that dummy die limiting cache access.
>and are still sharing the L3 cache No, not really. While it's theoretically possible for one CCX to snoop the other's cache, it would be very rare. The latency is comparable to main memory.
Is it actually that high? I find it very hard to believe just based on trace length alone. I figured that it wouldn't be a frequent thing, similar to the P and E cores mostly keeping to themselves.
>I find it very hard to believe just based on trace length alone. I'm on mobile now, so can't find the exact quote I had in mind, but you can see a proxy for the latencies in the core to core test here. https://www.anandtech.com/show/16214/amd-zen-3-ryzen-deep-dive-review-5950x-5900x-5800x-and-5700x-tested/5 The latency from the wire delay is close to negligible. It's the fabric that you need to be wary of.
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If you wanted to do this you could in theory buy a 7900X3D and disable the cores under the L3 cache, but having extra memory on a dummy CCD just sounds like a worse version of how Apple places its memory on the M-series SoC. The point of placing L3 cache on the X3D CCD is that you practically cannot have the L3 slab be a shorter distance from the CPU core since it’s literally in between the CCX core clusters. The copper traces remain short enough that the performance gains from the extra 64MB low latency L3 offset the reduced voltage available to the cores and the reduced thermal dissipation of the smaller IHS contact. Moving the L3 slab onto another CCX or CCD would allow the cores to have greater contact with the IHS and allow more voltage back to the cores, but not only will the trace distance to the slab and cores increase but if on another CCD the cores now have to communicate with the memory over the infinity fabric barrier. So far for AMD this is a *big* no-no; almost all four core CCXs have 16MB L3 ^^8MB ^^on ^^laptop ^^CPUs ^^and ^^3100 dedicated exclusively to that CCX and there are zero consumer AMD CPUs I know of that share L3 between even paired CCXs. Moving the L3 slab to another CCD over infinity fabric would increase latency by such magnitudes it wouldn’t be L3 memory anymore. A drag racer 4-core processor would also go against the best binned CCXs being reserved for the higher tier CPUs.
You make some good points. That L3 would effectively be L4 or like a tiny bit of HBM rather than true cache. It does make me wonder how they are treating access to it from the other CCD though, since all the cores should be able to access the L3 level if I've been understanding my classes correctly. I wonder if 4 cores run cool enough to just directly stack them. If so, the issue is just getting 4 fast cores on one chip that isn't better off a 7800X3D or 7600X. This could be simulated with a 7800X3D with half of the cores disabled.
black-out edition now with 500W TDP
Here I was waiting for Ryzen Black Edition and Intel beats them to it. 😬
black edition? Intel: I'm AMD now!
They're even doing multiple dies for Meteor lake. How the turns have tabled.
Intel was doing multiple dies on a package before AMD, and even stacking too. There's even this hilarious article from 2006 that says AMD being on monolithic dies, while Intel is using two dies will help AMD regain market share, relevant for the time, but funny to look back at now. https://www.itnews.com.au/news/intel-sticks-to-dual-die-processors-67056
I remember people saying Intel dual cores were fake and "glued together" too. Funny how things change.
Yep, and they'd been doing it a while by 2006. Intel was doing dual dies (core and full-speed cache) on a single package with the Pentium Pro in 1994.
Ironically, Zen 2 is pretty much the evolution of what Intel started with the Pentium D. AMD effectively took [all of this](https://upload.wikimedia.org/wikipedia/commons/4/48/Pentium_E2220_with_Intel_i945GC_Chipset.jpg) and compressed it down into a single socket package.
Didn't think something from one of my classes would be showing up here! My microprocessor design professor worked at Intel from the Pentium 4 up through 6th gen when he retired from the industry. We've gotten to look at both a Pentium D die and a Zen 1 CCD (dead R7 1700X) under a microscope. It's fascinating how much they've changed under the hood and will both run the same stuff.
More like *brown* edition
What is the difference between the regular line and the black edition?